The present invention relates to a converter, and more particularly, to a multiphase DC-DC converter.
FIG. 1 is a schematic block circuit diagram of a current-mode DC-DC converter 100. The converter 100 includes a control unit 1a and a converter unit 50. The converter unit 50 includes an output transistor T1 formed by an N-channel MOS transistor, a synchronous rectifying transistor T2 formed by an N-channel MOS transistor, a choke coil L1, a current detection resistor Rs1, and a smoothing capacitor C1.
The control unit 1a generates output signals DH1 and DL1, which are complementary signals, and provides the output signal DH1 to the gate of the output transistor T1 and the output signal DL1 to the gate of the synchronous rectifying transistor T2.
An input voltage Vi is supplied to the drain of the output transistor T1. When the output signal DH1 rises to an H level, the output transistor T1 is activated, and an output voltage Vo is output from an output terminal via the choke coil L1 and the current detection resistor Rs1. When the output signal DL1 rises to H level, the synchronous rectifying transistor T2 is activated, and the energy stored in the choke coil L1 is output as the output voltage Vo. The output voltage Vo is smoothed by the smoothing capacitor C1.
The input voltage Vi is supplied to the control unit 1a as voltage from a power source Vcc. A voltage amplifier 2 of the control unit 1a is supplied with the voltage between the two terminals of the current detection resistor Rs1. The voltage amplifier 2 amplifies the voltage generated between the terminals of the current detection resistor Rs1 in accordance with output current flowing through the current detection resistor Rs1 and provides an amplified signal to a comparator 3.
The control unit 1a has an error amplifier 4 for amplifying the voltage difference between a reference voltage e1 and a voltage obtained by dividing the output voltage Vo with resistors R1 and R2. Then, the error amplifier 4 provides the amplified signal to the comparator 3. The reference voltage e1 is set to be equal to the divided voltage generated by the resistors R1 and R when the output voltage Vo reaches a specified value.
The comparator 3 compares the voltage of the amplified signal provided from the voltage amplifier 2 with the voltage of the amplified signal provided from the error amplifier 4. When the voltage of the amplified signal from the voltage amplifier 2 is higher than that of the amplified signal from the error amplifier 4, the comparator 3 provides an H level comparison signal to the reset terminal R of a flip-flop circuit FF1. When the voltage of the amplified signal from the voltage amplifier 2 is lower than that of the amplified signal from the error amplifier 4, the comparator 3 provides an L level comparison signal to the reset terminal R.
A pulse signal with a fixed frequency is provided to the set terminal S of the flip-flop circuit FF1 by an oscillator 5. When the set terminal S receives an H level pulse signal, the flip-flop circuit FF1 generates an H level output signal Q and an L level output signal /Q. When the reset terminal R receives an H level comparison signal, the flip-flop circuit FF1 generates an L level output signal Q and an H level output signal /Q. The control unit 1a outputs the output signal Q of the flip-flop circuit FF1 as the output signal DH1 and the output signal /Q as the output signal DL1.
In response to a rising edge of the pulse signal from the oscillator 5, the control unit 1a turns the output transistor T1 on at constant cycles. When the output transistor T1 is activated, the current flowing through the choke coil L1 and the current detection resistor Rs increases to raise the voltage of the amplified signal from the voltage amplifier 2. When the voltage of the amplified signal from the voltage amplifier 2 becomes higher than the voltage of the amplified signal from the error amplifier 4, an H level output signal is provided to the reset terminal R of the flip-flop circuit FF1. As a result, the output transistor T1 is inactivated, the synchronous rectifying transistor T2 is activated, and the energy stored in the choke coil L1 is output.
If the output voltage Vo decreases during the on/off operation of the output transistor, the voltage of the amplified signal from the error amplifier 4 becomes higher than the voltage of the amplified signal of the voltage amplifier 2, and the output signal of the comparator 3 rises to an H level only after a relatively long time elapses. This prolongs the activation time of the output transistor T1. If the output voltage Vo increases, the voltage of the amplified signal from the error amplifier 4 becomes lower than the voltage of the amplified signal from the voltage amplifier 2, and the output signal of the comparator 3 rises to H level in a relatively short period of time. This shortens the activation time of the output transistor T1. The output transistor T1 is thus activated at constant cycles in accordance with the output signal frequency of the oscillator 5. The timing at which the output transistor T1 is inactivated is determined in accordance with the increase of the output current. The inactivation timing of the output transistor thus changes in accordance with the increase or decrease of the output voltage Vo. This keeps the output voltage Vo constant.
FIG. 2 is a schematic block circuit diagram of a voltage-mode DC-DC converter 200. The converter 200 includes a control unit 1b and a converter unit 60. The converter unit 60 has the same configuration as the converter unit 50 in FIG. 1 except in that the current detection resistor Rs1 is omitted.
An error amplifier 4 of the control unit 1b amplifies a voltage difference between a reference voltage e1 and a voltage obtained by dividing an output voltage Vo with resistors R1 and R2. Then, the error amplifier 4 provides the amplified signal to a non-inverting input terminal of a PWM comparator 6. The reference voltage e1 is set to be equal to the divided voltage generated by the resistors R1 and R2 when the output voltage Vo reaches a specified value.
A triangular wave signal with a fixed frequency is provided to an inverting input terminal of the PWM comparator 6 from a triangular wave oscillator 7. When the voltage of the amplified signal at the non-inverting input terminal is higher than the voltage of the triangular wave signal at the inverting input terminal, the PWM comparator 6 generates an H level output signal Q and an L level output signal /Q. When the voltage of the amplified signal at the non-inverting input terminal is lower than the voltage of the triangular wave signal at the inverting input terminal, the PWM comparator 6 generates an L level output signal Q and an H level output signal /Q.
The PWM comparator 6 provides the output signal Q to the gate of the output transistor T1 as an output signal DH1 of the control unit 1b and the output signal /Q to the gate of the synchronous rectifying transistor T2 as an output signal DL1 of the control unit 1b. 
In the voltage-mode DC-DC converter 200, the output transistor T1 is activated at constant cycles in accordance with the triangular wave signal from the triangular wave oscillator 7. When the output voltage Vo increases, the output voltage of the error amplifier 4 is decreased to shorten the activation time of the output transistor T1. When the output voltage Vo decreases, the output voltage of the error amplifier 4 is increased to prolong the activation time of the output transistor T1. Such operation keeps the output voltage Vo constant based on the reference voltage e1.
FIG. 3 is a schematic block circuit diagram of a fixed activation time DC-DC converter 300. The converter 300 includes a control unit 1c and a converter unit 60.
A comparator 8 of the control unit 1c compares a reference voltage e1 with a voltage obtained by dividing the output voltage Vo resistors R1 and R2. When the divided voltage generated by the resistors R1 and R2 is higher than the reference voltage e1, the comparator 8 generates an L level comparison signal. When the divided voltage is lower than the reference voltage e1, the comparator 8 generates an H level comparison signal. The reference voltage e1 is set to be equal to the divided voltage generated by the resistors R1 and R2 when the output voltage Vo reaches a specified value.
The comparison signal of the comparator 8 is provided to a one-shot flip-flop circuit FF. The one-shot flip-flop circuit FF generates complementary signals Q and /Q in accordance with the comparison signal. The one-shot flip-flop circuit FF keeps the output signal Q at an H level for a predetermined period of time in response to an H level comparison signal from the comparator 8.
The output signal Q of the one-shot flip-flop circuit FF is provided to the gate of an output transistor T1 as an output signal DH1 of the control unit 1c. The output signal /Q is provided to the gate of a synchronous rectifying transistor T2 as an output signal DL1 of the control unit 1c. 
In the fixed activation time DC-DC converter 300, the output voltage Vo increases when the output transistor T1 is activated. When the output transistor T1 is inactivated, the energy stored in a choke coil L1 is discharged. The decrease of the energy stored in the choke coil L1 lowers the output voltage Vo. When the divided voltage generated by the resistors R1 and R2 becomes lower than the reference voltage e1, the one-shot flip-flop circuit FF generates an H level output signal Q for a predetermined period of time. Thus, the output transistor T1 is activated.
This operation keeps the output signal Vo based on the reference voltage e1 constant. In the converter 300, the activation time of the output transistor T1 is fixed regardless of changes in the output voltage Vo. However, a decrease in the output voltage Vo shortens the inactivation time of the output transistor T1. Thus, the switching frequency of the output transistor T1 changes in accordance with the output voltage Vo.
FIG. 4 is a schematic block circuit diagram of a two-phase multiphase DC-DC converter 400 in which two current-mode DC-DC converters 100 of FIG. 1 are operated in parallel. The converter 400 includes a control unit 1d and converter units 9a and 9b. Each of the converter units 9a and 9b has the same configuration as the converter unit 50 in FIG. 1. The converter units 9a and 9b share a single smoothing capacitor C1.
The control unit 1d includes a voltage amplifier 2a for amplifying the voltage between the two terminals of a current detection resistor Rs1 of the converter unit 9a, a voltage amplifier 2b for amplifying the voltage between the two terminals of a current detection resistor Rs2 of the converter unit 9b, a comparator 3a for comparing the output voltage of the voltage amplifier 2a with the output voltage of the error amplifier 4, and a comparator 3b for comparing the output voltage of the voltage amplifier 2b with the output voltage of the error amplifier 4. The control unit 1d further includes a flip-flop circuit FF1, for generating output signals DH1 and DL1 that control the converter unit 9a in accordance with the comparison signal of the comparator 3a, and a flip-flop circuit FF2, for generating output signals DH2 and DL2 that control the converter unit 9b in accordance with the comparison signal of the comparator 3b. 
An oscillator 5a provides a pulse signal to the set terminals S of the flip-flop circuits FF1 and FF2. More specifically, the oscillator 5a generates a pulse signal with a frequency that is twice the frequency of the oscillator 5 in FIG. 1 and provides the pulse signal alternately to the flip-flop circuits FF1 and FF2.
The control unit id operates the converter units 9a and 9b in the same manner and at the same frequency as the converter unit 50 of the current-mode DC-DC converter 100 in FIG. 1. However, since the operational phases of the flip-flop circuits FF1 and FF2 are offset 180 degrees from each other, the converter 400 operates a load with a frequency that is substantially two times greater.
FIG. 5 is a schematic block circuit diagram of a two-phase multiphase DC-DC converter 500 in which two fixed activation time DC-DC converters of FIG. 3 are operated in parallel. The converter 500 includes a control unit 1e and converter units 10a and 10b. Each of the converter units 10a and 10b has the same configuration as the converter unit 60 of FIG. 3. The converter units 10a and 10b share a single smoothing capacitor C1.
The control unit 1e includes resistors R1 and R2 for dividing the output voltage Vo, a comparator 8 for comparing the divided voltage generated by the resistors R1 and R2 with a reference voltage e1, and an order control circuit 11 for alternately outputting a comparison signal generated by the comparator 8 to two one-shot flip-flop circuits FFa and FFb. The one-shot flip-flop circuit FFa generates output signals DH1 and DL1 for controlling the converter unit 10a. The one-shot flip-flop circuit FFb generates output signals DH2 and DL2 for controlling the converter unit 10b. 
The control unit 1e operates the converter units 10a and 10b in the same manner as the converter unit 60 of the fixed activation time DC-DC converter 300 in FIG. 3. However, the respective output transistors T1 of the converter units 10a and 10b are activated alternately by the order control circuit 11. Therefore, in the converter 500, the inactivation time of the output transistors T1 is longer than in the converter 400 of FIG. 3. This enables substantial decrease of the switching frequency of the output transistors T1. Additionally, when the output voltage Vo suddenly decreases due to a change in the load, the output transistors T1 of the converter units 10a and 10b are successively activated in accordance with the response speed of the comparator 8. The DC-DC converter 500 has superior response speed when the load suddenly changes.
Japanese Patent Laid-Open Publication No. 2002-78321 describes a DC-DC converter similar to the above DC-DC converter.